Power-Intent Integration into the Digital System Specification Model

Power consumption is becoming the key aspect in modern digital systems design. The current low-power design flow involves the application of some power-reduction techniques in an RTL (Register Transfer Level) or lower-level model. This paper describes a novel methodology for low-power design flow that supplements the existing one. It proposes an abstract form of the power-intent specification based on UPF (Unified Power Format) and integrates it into a systemlevel model. Power-intent specification at such an abstract level enables to manage power with higher efficiency, since power-aware decisions at this stage have more impact on eventual power consumption.